1 BCM datasheet errata. the BCM Broadcom specifies the reserved bits the other way around: “Write zeroes, read: don’t care”. Read about ‘Broadcom: Datasheet for BCM ARM Peripherals’ on element14 .com. Broadcom: Datasheet for BCM ARM Peripherals. If you have been following Raspberry Pi project, you may have noticed the dearth of documentation related to Broadcom processors.

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The IO register is documented as 0x7ea0 with automatic deassert and 0x7eb0, whereas the table on page 8 shows 0x7e The hardware was changed detecting “half full” was difficult? If 1 the data is shifted in starting with the MS bit. If you follow the datasheet, and write zeroes as specified to the reserved bits, the hardware guys can make sure you’re not going to run into surprises.

I dunno the official answer to this, but the community-written SPI drivers here and here set them both at the same time. The register reads as 0x after reset. Allusions to the APB clock domain are made. It also “does the right thing” with reserved bits. Another hint is that it says that the bit clears when “sufficient” data is read from the FIFO. Link to it via two control blocks on the primary chain.

Or the hardware does what I expect: Thus new data is concatenated to old data. The word sufficient is redundant when this is the “full and active” bit. The divider is split between an integer divider and a fractional mashing divider. This bit would be useful if it signified more than half full. Views Read View source View history. I think- not confirmed. I assume you want the cleanest clock source which is the XTAL Near the bottom of the page RXR. Not as “half the maximum”.

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If 1 the receiver shift register is NOT cleared.

Possibly the “choice” hasn’t been specified. This had lead to a confusing picture. This is from Geert Van Loos at the page below:. Privacy policy About dtasheet.

This is confusing as indeed there is a different module called SPI0 documented on page and onwards. This is not true. Does this mean, that the SYNC bit can also be changed at runtime as well? However, bits 7 and 9 does not match the original datasheet, nor my guess How datasyeet these combine???

Not really an erratum, but not worth it to make a whole page for this. A detailed analysis of this bug can be found at http: There is amiguity on what register bits can be modified while the I2S system is active.

BCM Datasheet(PDF) – Broadcom Corporation.

If you expand the hardware the hardware may be enhanced and do “different things” if you write ones to the previously “reserved” bits. There is a bug in the I2C master that broadckm does not support clock stretching at arbitrary points.

There is a space in ” full ” that would hint at that the bcm22835 “half” was taken away. The table, legend for tablebroadcoom on page shows twice in red: Under rare situations this may result in “lost” clocks while MOSI still shifts out the data!


The way it is written now, this bit is just the same as bit RXF, except that the TA bit is anded into this one. Some of the tables from the datasheet have been reproduced here. Instead of “when all register contents is lost. They should both read “If this bit cleared no new symbols will be However the exact speed of the APB clock is never explained.

The Peek register is documented here as being at 0x7ec, whereas the table on page 8 shows 0x7e Two bits high would be consistent with TX empty and RX empty. The bottom bit doesn’t work as per specifications, and because the “0” results inthe top datashheet doesn’t either.

BCM2835 datasheet errata

The partial datasheet was published here: An easy implementation would implement the 0 value as the maximum divisor. Many datasheets specify “write: In table the values in columns “min output freq” and “max output freq” should be in each others. Retrieved from ” https: Navigation menu Personal tools Log in Request account.